The present invention relates, in general, to a technique of fabricating an ultra large-scale integration (VLSI) circuits, and more particularly, to a method of fabricating a borderless via.
During manufacturing of a semiconductor integrated circuit, electrically conductive materials patterned in electrical circuitry are layered over a base transistor structure that is disposed on a semiconductor substrate. The electrically conductive materials, such as aluminum or copper, are in different and noncontiguous planes. Vias or pathways connect the various layers of electrically conductive materials.
Referring to FIGS. 1A through 1D, the cross-sectional Aside views of a conventional method of fabricating a borderless via are depicted in sequence.
Referring now to FIG. 1A, a first dielectric layer 15 is formed on a semiconductor substrate 10 consisting of mono-crystal silicon. A metallic plug 17 is filled in a via 16 which is formed through the first dielectric layer 15. Then, a first conductive structure 11b and a second conductive structure 11a, such as aluminum or aluminum-copper alloy, serving as interconnects are formed on the first dielectric layer 15. In addition, the area of the second conductive structure 11a is much smaller than that of the first conductive structure 11b. 
Next, as shown in FIG. 1B, a second dielectric layer 20 is coated over the first dielectric layer 15. The second dielectric layer 20 is organic low dielectric constant (low k) material (for example k less than 4), the organic low k material can result in an uneven surface of the second dielectric layer 20 since the thickness d1 above the first conductive structure 11b is larger than the thickness d2 above the second conductive structure 11a. 
As shown in FIG. 1C, the second dielectric layer 20 is etched back to leave a second dielectric layer 20a, which can be served as an etching-stop layer and has a very thin thickness.
Referring now to FIG. 1D, a third dielectric layer 40 is formed over the second dielectric layer 20a. After that, borderless vias 52, 54 are formed by selective removal of the third dielectric layer 40.
However, the formation of the second dielectric layer 20a that serves as an etching-stop layer is difficult to control. The remaining second dielectric layer 20a upon the first conductive structure 11b with large area can cause disconnect of the various layers of electrically conductive materials. On the other hand, it can also cause inappropriate connection (short) between metallic plug 17 and a conductive material filling within the via 52 in the subsequent step.
In view of the above disadvantages, an object of the invention is to provide a method of fabricating a borderless via so as to form a desirable and appropriate etching stop layer consisting of a portion of second dielectric layer.
Another object of the invention is to provide a method of fabricating a borderless via so that the dielectric material disposed on the conductive structures is substantially removed thereby eliminating the troubles of the prior art.
The above object is attained by providing a method of fabricating a borderless via, comprising the steps of: providing a substrate having a first dielectric layer thereon; forming a first conductive structure and a second conductive structure whose area is smaller than said first conductive structure on said first dielectric layer; forming a second dielectric layer with an uneven surface over said first conductive structure and said second conductive structure; coating a planarizing layer over said second dielectric layer to fill said uneven surface; etching back said planarizing layer and a part of said second dielectric layer so that the upper surface of said second dielectric layer is lower than the upper surfaces of said first conductive structure and said second conductive structure; forming a third dielectric layer over said second dielectric layer; and selectively etching said third dielectric layer until said second dielectric layer is exposed to create a borderless via.
Furthermore, in the method of fabricating a borderless via according to the present invention, the first conductive structure and the second conductive structure can comprise materials selected from the group consisting of aluminum, copper, tungsten, silver, gold, and their respective alloys.
Furthermore, in the method of fabricating a borderless via according to the present invention, the first dielectric layer and the third dielectric layer can comprise oxide such as silicon dioxide formed by CVD.
Furthermore, in the method of fabricating a borderless via according to the present invention, the second dielectric layer can comprise organic low dielectric constant (low k, for example k less than 3) material such as fluorinated poly (arylene ether) polymer (FLARE(trademark)) or SiLK produced by Dow Chemical Company. Moreover, the planarizing layer can comprise organic photoresist, anti-reflection coating (BARC), or inorganic spin-on-glass (SOG).
In addition, in the method of fabricating a borderless via according to the present invention, the third dielectric layer has an etch selectivity of about 5:1 to about 10:1 with respect to the second dielectric layer. Also, the planarizing layer, such as organic photoresist, BARC, has an etch selectivity of about 1:1 with respect to said second dielectric layer. In addition, the planarizing layer, such as SOG, has an etch selectivity of about 1:3xcx9c1:5 with respect to said second dielectric layer.
Furthermore, in the method of fabricating a borderless via according to the present invention can further comprise a step of filling a conductive material, such as tungsten, within the borderless via to create a conductive plug.